Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 9/26/2022
Public
Document Table of Contents

3.2.2.4. Step 4: Create a Tile Plan

Click Plan Design on the Flow control to interactively place component IP in legal locations on device tiles. The Plan tab displays a hierarchical list of your project component IP design elements, alongside a graphical abstraction of the target device tile architecture. Place IP (and IP building blocks) in legal tile locations within the graphical tile floorplan.
Tile Interface Planner Design Elements and Chip View

Recommended Two-Stage Tile IP Placement

Handle IP tile placement in two stages for the most efficiency:

Table 17.  Two-Stage Tile IP Placement
Tile IP Placement Description
Stage 1
  • Place all of the IPs targeting the same tile to ensure that all IP can be placed within the tile, as Placing IP Components describes.
  • Fill each tile with the desired IP, before refining any IP building block placement for any specific placement requirements you may have for a particular building block.
Stage 2
  • Review the placement of IP building blocks.
  • Refine any building block placement to meet any specific placement requirements, as Constraining IP Building Blocks describes.
Note: Changes made in Tile Interface Planner do not apply to your Intel® Quartus® Prime project until you apply the generated tile interface plan constraints to your project, as Step 5: Save Tile Plan Assignments describes.

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