Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 9/26/2022
Public
Document Table of Contents

3.2.2.1. Step 1: Instantiate IP and Run Design Analysis

Tile Interface Planner requires an Intel® Quartus® Prime project that includes component IP targeting the Intel® Agilex™ FPGA with F-tile.

After instantiating the component IP in a top-level project design file (for example, top.v), you run the Design Analysis compilation stage to elaborate the design RTL to extract component IP and target device information. Upon launch, Tile Interface Planner initializes and displays this component IP information in the Design Tree view.

Follow these steps to instantiate IP and run Design Analysis:
  1. Open or create an Intel® Quartus® Prime project that includes component IP targeting F-tile:
    • Create a new project, add design files, and specify the target Intel® Agilex™ FPGA by clicking File > New Project Wizard.

      Or

    • Parameterize and instantiate component IP with IP Catalog (View > IP Catalog) or Platform Designer (Tools > Platform Designer ).
  2. To run the Design Analysis stage of the Compiler, double-click Design Analysis on the Compilation Dashboard (Processing > Compilation Dashboard).
    Figure 26. Design Analysis Stage in Compilation Dashboard
  3. Initialize Tile Interface Planner, as Step 2: Initialize Tile Interface Planner describes.

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