18.104.22.168. Specify Instance-Specific Constraints in Assignment Editor 22.214.171.124. Specifying Multi-Dimensional Bus Constraints 126.96.36.199. Specify I/O Constraints in Pin Planner 188.8.131.52. Plan Interface Constraints in Interface Planner and Tile Interface Planner 184.108.40.206. Adjust Constraints with the Chip Planner 220.127.116.11. Constraining Designs with the Design Partition Planner
18.104.22.168. Specifying Near-End vs Far-End I/O Timing Analysis
You can select a near-end or far-end point for I/O timing analysis. Near-end timing analysis extends to the device pin. You can apply the set_output_delay constraint during near-end analysis to account for the delay across the board.
With far-end I/O timing analysis, the advanced I/O timing analysis extends to the external device input, at the far-end of the board trace. Whether you choose a near-end or far-end timing endpoint, the board trace models are taken into account during timing analysis.
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