22.214.171.124. Specify Instance-Specific Constraints in Assignment Editor 126.96.36.199. Specifying Multi-Dimensional Bus Constraints 188.8.131.52. Specify I/O Constraints in Pin Planner 184.108.40.206. Plan Interface Constraints in Interface Planner and Tile Interface Planner 220.127.116.11. Adjust Constraints with the Chip Planner 18.104.22.168. Constraining Designs with the Design Partition Planner
3.2.3. Constraining Dynamic Reconfiguration IP
Tile Interface Planner and Tile Assignment Editor provide support for constraining IP instances that are part of a dynamic reconfiguration group.
Dynamic reconfiguration allows you to modify some features of an Intel® FPGA IP interface in real time, while the FPGA remains in continuous operation. This dynamic reconfiguration capability allows you to change your design to run at different data rates, and with different features, for different IP "profiles."
When you generate a dynamically reconfigurable IP instance, the IP includes a .mif file that specifies the base and secondary profiles that you define. Each profile contains the delta programming sequences for the dynamic reconfiguration of the IP in a linked-list format.
Defining a Dynamic Reconfiguration Group
Assigning Dynamic Reconfiguration Group Placement
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