Visible to Intel only — GUID: iga1405460037726
Ixiasoft
Visible to Intel only — GUID: iga1405460037726
Ixiasoft
11.3.1.5. Synchronizer Stages
The option Synchronizer Stages allows you to specify the length of synchronization register chains. These register chains are used when a metastable event is likely to occur and the length specified determines the meantime before failure. The register chain length, however, affects the latency of the core.
For more information on metastability in Intel FPGA devices, refer to Understanding Metastability in FPGAs.
For more information on metastability analysis and synchronization register chains, refer to the Area and Timing Optimization chapter in volume 2 of the Intel® Quartus® Prime Handbook.