Embedded Peripherals IP User Guide

ID 683130
Date 2/09/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

54.5. Interface Signals

Table 493.  Interface Signals for FIXED, GPIO and CSR mode
Signal Names Direction Description
ACE-LITE Manager
axm_m0_araddr Output The address of the first transfer in a read transaction.
axm_m0_arbar Output Provides information on barrier type in a read transaction.
axm_m0_arburst Output Burst type. Indicates how the address changes between each transfer in a read transaction.
axm_m0_arcache Output Indicates how a read transaction is required to progress though a system.
axm_m0_ardomain Output Provides information on shareability domain in a read transaction.
axm_m0_arid Output Identification tag for a read transaction.
axm_m0_arlen Output The exact number of data transfer in a read transaction.
axm_m0_arlock Output Provides information about the atomic characteristics of a read transaction.
axm_m0_arprot Output Protection attributes of a read transaction: privilege, security level, and access type.
axm_m0_arqos Output Quality of service indentifier for a read transaction.
axm_m0_arready Input Indicates that a transfer on the read address channel can be accepted.
axm_m0_arsize Output The number of bytes in each data transfer in a read transaction.
axm_m0_arsnoop Output Indicates the transaction type in a shareable read transaction.
axm_m0_aruser Output User-defined extension for the read address channel.
axm_m0_arvalid Output Indicates valid read address channel signals.
axm_m0_awaddr Output The address of the first transfer in a write transaction
axm_m0_awbar Output Provides information on barrier type in a write transaction.
axm_m0_awburst Output Burst type. Indicates how address changes between each transfer in a write transaction.
axm_m0_awcache Output Indicates how a write transaction is required to progress through a system.
axm_m0_awdomain Output Provides information on shareability domain in a write transaction.
axm_m0_awid Output Identification tag for a write transaction.
axm_m0_awlen Output The exact number of data transfer in a write transaction. This information determines the number of data transfers associated with the address.
axm_m0_awlock Output Provides information about the atomic characteristics of a write transaction.
axm_m0_awprot Output Protection attributes of a write transactions: privilege, security level, and access type.
axm_m0_awqos Output Quality of Service identifier for a write transaction.
axm_m0_awready Input Indicates that a transfer on the write address channel can be accepted.
axm_m0_awsize Output The number of bytes in each data transfer in a write transaction.
axm_m0_awsnoop Output Indicates the transaction type in a shareable write transaction.
axm_m0_awuser Output User-defined extension for the write address channel.
axm_m0_awvalid Output Indicates valid write address channel signals.
axm_m0_bid Input Identification tag for a write response.
axm_m0_bready Output Indicates that a transfer on the write response channel can be accepted.
axm_m0_bresp Input Indicates the status of a write transaction.
axm_m0_bvalid Input Indicates valid write response response channel signals.
axm_m0_rdata Input Read data.
axm_m0_rid Input Identification tag for read data and response.
axm_m0_rlast Input Indicates whether this is the last data transfer in a read transaction.
axm_m0_rready Output Indicates that a transfer on the read data channel can be accepted.
axm_m0_rresp Input Indicates the status of a read transfer.
axm_m0_rvalid Input Indicates valid the read data channel signals.
axm_m0_wdata Output Write data.
axm_m0_wlast Output Indicates whether this is the last data transfer in a write transaction.
axm_m0_wready Input Indicates that a transfer on the write data channel can be accepted.
axm_m0_wstrb Output Write strobes. Indicates which byte lanes hold valid data.
axm_m0_wvalid Output Indicates valid write data channel signals.
AXI-4 Subordinate
axs_s0_araddr Output The address of the first transfer in a read transaction.
axs_s0_arburst Output Burst type. Indicates how the address changes between each transfer in a read transaction.
axs_s0_arcache Output Indicates how a read transaction is required to progress through a system.
axs_s0_arid Output Identification tag for a read transaction.
axs_s0_arlen Output The exact number of data transfers in a read transaction.
axs_s0_arlock Output Provides information about the atomic characteristics of a read transaction.
axs_s0_arprot Output Protection attributes of a read transaction: privilege, security level, and access type.
axs_s0_arready Output Indicates that a transfer on the read address channel can be accepted.
axs_s0_arsize Output The number of bytes in each data transfer in a read transaction.
axs_s0_arvalid Output Indicates valid read address channel signals.
axs_s0_awaddr Input The address of the first transfer in a write transaction.
axs_s0_awburst Output Burst type. Indicates how the address changes between each transfer in a write transaction.
axs_s0_awcache Output Indicates how a write transaction is required to progress through a system.
axs_s0_awid Output Identification tag for a write transaction.
axs_s0_awlen Output The exact number of data transfers in a write transaction. This information determines the number of data transfers associated with the address.
axs_s0_awlock Output Provides information about the atomic characteristics of a write transaction.
axs_s0_awprot Output Protection attributes of a write transactions: privilege, security level, and access type.
axs_s0_awready Output Indicates that a transfer on the write address channel can be accepted.
axs_s0_awsize Output The number of bytes in each data transfer in a write transaction.
axs_s0_awvalid Output Indicates valid write address channel signals.
axs_s0_bid Output Identification tag for a write response.
axs_s0_bready Output Indicates that a transfer on the write response channel can be accepted.
axs_s0_bresp Output Write response. Indicates the status of a write transaction.
axs_s0_rdata Output Read data.
axs_s0_rid Input Identification tag for read data and response.
axs_s0_rlast Output Indicates whether this is the last data transfer in a read transaction.
axs_s0_rready Output Indicates that a transfer on the read data channel can be accepted.
axs_s0_rresp Output Read response. Indicates the status of a read transfer.
axs_s0_rvalid Output Indicates valid read data channel signals.
axs_s0_wdata Input Write data.
axs_s0_wlast Output Indicates whether this is the last data transfer in a write transaction.
axs_s0_wready Input Indicates that a transfer on the write data channel can be accepted.
axs_s0_wstrb Input Write strobes. Indicates which byte lanes hold valid data.
axs_s0_wvalid Input Indicates valid write data channel signals.
Table 494.  Interface Signals for CSR mode
Signal Names Direction Description
CSR Avalon® memory-mapped
addr Input Address
read Input Read
write Input Write
writedata Input Write Data
readdata Output Read Data
Table 495.  Interface Signals for GPIO mode
Signal Names Direction Description
GPIO Conduit
gp_output Input HPS gp_output
gp_input Output HPS gp_input