Embedded Peripherals IP User Guide

ID 683130
Date 2/09/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

32.6.4. DMA Descriptors

See the Data Structure section for the structure definition.
Table 358.  DMA Descriptor Structure
Byte Offset Field Names
31   24 23   16 15    8 7   0
base source
base + 4 Reserved
base + 8 destination
base + 12 Reserved
base + 16 next_desc_ptr
base + 20 Reserved
base + 24 Reserved bytes_to_transfer
base + 28 desc_control desc_status actual_bytes_transferred
Table 359.  DMA Descriptor Field Description
Field Name Access Description
source R/W Specifies the address of data to be read. This address is set to 0 if the input interface is an Avalon® -ST interface.
destination R/W Specifies the address to which data should be written. This address is set to 0 if the output interface is an Avalon® -ST interface.
next_desc_ptr R/W Specifies the address of the next descriptor in the linked list.
bytes_to_transfer R/W Specifies the number of bytes to transfer. If this field is 0, the SG-DMA controller core continues transferring data until it encounters an EOP.
actual_bytes_transferred R Specifies the number of bytes that are successfully transferred by the core. This field is updated after the core processes a descriptor.
desc_status R/W This field is updated after the core processes a descriptor. See DESC_STATUS Bit Map for the bit map of this field.
desc_control R/W Specifies the behavior of the core. This field is updated after the core processes a descriptor. See the DESC_CONTROL Bit Map table for descriptions of each bit.
Table 360.  DESC_CONTROL Bit Map
Bit (s) Field Name Access Description
0 GENERATE_EOP W When this bit is set to 1,the DMA read block asserts the EOP signal on the final word.
1 READ_FIXED_ADDRESS R/W This bit applies only to Avalon® -MM read host ports. When this bit is set to 1, the DMA read block does not increment the memory address. When this bit is set to 0, the read address increments after each read.
2 WRITE_FIXED_ADDRESS R/W This bit applies only to Avalon® -MM write host ports. When this bit is set to 1, the DMA write block does not increment the memory address. When this bit is set to 0, the write address increments after each write.

In memory-to-stream configurations, the DMA read block generates a start-of-packet (SOP) on the first word when this bit is set to 1.

[6:3] Reserved
3 .. 6 AVALON-ST_CHANNEL_NUMBER R/W The DMA read block sets the channel signal to this value for each word in the transaction. The DMA write block replaces this value with the channel number on its sink port.
7 OWNED_BY_HW R/W This bit determines whether hardware or software has write access to the current register.

When this bit is set to 1, the core can update the descriptor and software should not access the descriptor due to the possibility of race conditions. Otherwise, it is safe for software to update the descriptor.

After completing a DMA transaction, the descriptor processor block updates the desc_status field to indicate how the transaction proceeded.

Table 361.  DESC_STATUS Bit Map
Bit Bit Name Access Description
[7:0] ERROR_0 .. ERROR_7 R Each bit represents an error that occurred on the Avalon® -ST interface. The context of each error is defined by the component connected to the Avalon® -ST interface.