Embedded Peripherals IP User Guide

ID 683130
Date 2/09/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

42.2.2. Operation

The Avalon® Packets to Transactions Converter core receives streams of packets on its Avalon® -ST sink interface and initiates Avalon® -MM transactions. Upon receiving transaction responses from Avalon® -MM agents, the core transforms the responses to packets and returns them to the requesting components via its Avalon® -ST source interface. The core does not report Avalon® -ST errors.

Packet Formats

The core expects incoming data streams to be in the format shown in the table below. A response packet is returned for every write transaction. The core also returns a response packet if a no transaction (0x7f) is received. An invalid transaction code is regarded as a no transaction. For read transactions, the core simply returns the data read.

Table 442.  Packet Formats
Byte Field Description
Transaction Packet Format
0 Transaction code Type of transaction. See Properties of Avalon® -ST Interfaces table.
1 Reserved Reserved for future use.
[3:2] Size Transaction size in bytes. For write transactions, the size indicates the size of the data field. For read transactions, the size indicates the total number of bytes to read.
[7:4] Address 32-bit address for the transaction.
[n:8] Data Transaction data; data to be written for write transactions.
Response Packet Format
0 Transaction code The transaction code with the most significant bit inversed.
1 Reserved Reserved for future use.
[3:2] Size Total number of bytes read/written successfully.

Supported Transactions

The table below lists the Avalon® -MM transactions supported by the core.

Table 443.  Transaction Supported
Transaction Code Avalon® -MM Transaction Description
0x00 Write, non-incrementing address. Writes data to the given address until the total number of bytes written to the same word address equals to the value specified in the size field.
0x04 Write, incrementing address. Writes transaction data starting at the given address.
0x10 Read, non-incrementing address. Reads 32 bits of data from the given address until the total number of bytes read from the same address equals to the value specified in the size field.
0x14 Read, incrementing address. Reads the number of bytes specified in the size field starting from the given address.
0x7f No transaction. No transaction is initiated. You can use this transaction type for testing purposes. Although no transaction is initiated on the Avalon® -MM interface, the core still returns a response packet for this transaction code.

The core can handle only a single transaction at a time. The ready signal on the core's Avalon® -ST sink interface is asserted only when the current transaction is completely processed.

No internal buffer is implemented on the data paths. Data received on the Avalon® -ST interface is forwarded directly to the Avalon® -MM interface and vice-versa. Asserting the waitrequest signal on the Avalon® -MM interface back-pressures the Avalon® -ST sink interface. In the opposite direction, if the Avalon® -ST source interface is back-pressured, the read signal on the Avalon® -MM interface is not asserted until the backpressure is alleviated. Back-pressuring the Avalon® -ST source in the middle of a read could result in data loss. In such cases, the core returns the data that is successfully received.

A transaction is considered complete when the core receives an EOP. For write transactions, the actual data size is expected to be the same as the value of the size field. Whether or not both values agree, the core always uses the EOP to determine the end of data.

Malformed Packets

The following are examples of malformed packets:

  • Consecutive start of packet (SOP)—An SOP marks the beginning of a transaction. If an SOP is received in the middle of a transaction, the core drops the current transaction without returning a response packet for the transaction, and initiates a new transaction. This effectively handles packets without an end of packet(EOP).
  • Unsupported transaction codes—The core treats unsupported transactions as a no transaction.