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10.2.7. FPGA Resource Usage
In order to optimize resource usage, in terms of register counts, the UART IP design specifically targets MLABs to be used as FIFO storage element. The following table lists the FPGA resources required for one UART with 128 Byte Tx and Rx FIFO.
Resource | Number |
---|---|
ALMS needed | 362 |
Total LABs | 54 |
Combinational ALUT usage for logic | 436 |
Combinational ALUT usage for route-throughs | 17 |
Dedicated logic registers
|
311 |
Global Signals | 2 |
M10k blocks | 0 |
Total MLAB memory bits | 2432 |