Visible to Intel only — GUID: lro1402071735548
Ixiasoft
Visible to Intel only — GUID: lro1402071735548
Ixiasoft
36.2. Feature Description
The ILC is made up of three sub functional blocks. The top level interface is Avalon® Memory Mapped ( Avalon® -MM) protocol compliant. The interrupt detector block will be activated by the rising edge of the interrupt signal or pulse, determined by a parameter during component generation. The interrupt detector block determines when to start or stop the 32-bit internal counter, which is reset to zero every time it begins operation without affecting previous stored latency data register value. The latency data register is updated after the counter is stopped.
Each counter can be configured to host up to 32 identical counters to monitor separate IRQ channels. Each counter only observes one interrupt input. The interrupt could be level sensitive or pulse (edge) sensitive. In the case where more interrupt lines need to be monitored, multiple counters could be instantiated in Platform Designer.
ILC only keeps track of the latest interrupt latency value. If multiple interrupts are happening in series, only the last interrupt latency will be maintained. On the other hand, every start of interrupt edge refreshes the internal counter from zero.