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Ixiasoft
3.3. Parameters
Parameter | Legal Values | Description |
---|---|---|
Bits per symbol | 1–32 | These parameters determine the width of the FIFO. FIFO width = Bits per symbol * Symbols per beat, where: Bits per symbol is the number of bits in a symbol, and Symbols per beat is the number of symbols transferred in a beat. |
Symbols per beat | 1–32 | |
Error width | 0–32 | The width of the error signal. |
FIFO depth | 1–32 | The FIFO depth. An output pipeline stage is added to the FIFO to increase performance, which increases the FIFO depth by one. |
Use packets | — | Turn on this parameter to enable packet support on the Avalon® -ST data interfaces. |
Channel width | 1–32 | The width of the channel signal. |
Avalon® -ST Single Clock FIFO Only | ||
Use fill level | — | Turn on this parameter to include the Avalon® -MM control and status register interface. |
Avalon® -ST Dual Clock FIFO Only | ||
Use sink fill level | — | Turn on this parameter to include the Avalon® -MM control and status register interface in the input clock domain. |
Use source fill level | — | Turn on this parameter to include the Avalon® -MM control and status register interface in the output clock domain. |
Write pointer synchronizer length | 2–8 | The length of the write pointer synchronizer chain. Setting this parameter to a higher value leads to better metastability while increasing the latency of the core. |
Read pointer synchronizer length | 2–8 | The length of the read pointer synchronizer chain. Setting this parameter to a higher value leads to better metastability. |
Use Max Channel | — | Turn on this parameter to specify the maximum channel number. |
Max Channel | 1–255 | Maximum channel number. |
For more information on metastability in Intel FPGA devices, refer to AN 42: Metastability in Intel FPGA devices.
For more information on metastability analysis and synchronization register chains, refer to the Area and Timing Optimization chapter in volume 2 of the Intel® Quartus® Prime Handbook.