Embedded Peripherals IP User Guide

ID 683130
Date 2/09/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

7.5.2.2. Capabilities and Configuration Registers

You can access these register using the GET_CONFIGURATION and SET_CONFIGURATION commands. When you configure the registers using the SET_CONFIGURATION command, the new register value takes affect only at the deassertion edge of espi_cs_n.

The capabilities and configuration register bits are reset by espi_reset_n.
Table 34.  Capabilities and Configuration Register Map
Offset Register Name
0x4 Device Identification
0x8 General Capabilities and Configurations
0x10 Channel 0 Capabilities and Configurations
0x20 Channel 1 Capabilities and Configurations
0x30 Channel 2 Capabilities and Configurations
0x40 Channel 3 Capabilities and Configurations
Table 35.  Device Identification Register Description
Bit Access Type Default Value Description
31:8 - - Reserved.
7:0 R 0x01 Indicates the Version ID that is compliant to the specific eSPI specification revision.
Table 36.  General Capabilities and Configurations Register Description
Bit Access Type Default Value Description
31 RW 0 CRC Checking:
  • 1: CRC checking is enabled
  • 0: CRC checking is disabled
30:29 - - Reserved.
28 RW 0 Alert Mode:
  • 1: espi_alert_n is used to signal the Alert event
  • 0: espi_data[1] is used to signal the Alert event
27:26 RW 2'b00 I/O Mode Select:
  • 2'b00: Single I/O
  • 2'b01: Dual I/O
  • 2'b10: Quad I/O
  • 2'b11: Reserved
25:24 R - Indicates value set for eSPI Mode of Operation parameter.
23 - - Reserved.
22:20 RW 3'b000 Operating Frequency:
  • 3'b000: 20MHz
  • 3'b001: 25MHz
  • 3'b010: 33MHz
  • 3'b011: 50MHz
  • 3'b100: 66MHz
19 - - Reserved.
18:16 R - Indicates value set for Frequency of Operation parameter.
15: 12 RW 4'b0000 The maximum Wait State allowed before responding with an ACCEPT, DEFER, NON_FATAL ERROR or FATAL ERROR response code:
  • 4'b0000: 16 byte time
  • 4'b0001: 1 byte time
  • 4'b0010: 2 byte time
  • 4'b0011: 3 byte time
  • .....
  • 4'b1111: 15 byte time
11:8 - - Reserved.
7:0 R - Indicates value set for Channel Supported parameter.
Table 37.  Channel 0 Capabilities and Configurations Register Description
Bit Access Type Default Value Description
31:15 - - Reserved.
14:12 RW 3'b001 Peripheral Channel Address Aligned Maximum Read Request Size:
  • 3'b000: Reserved
  • 3'b001: 64 bytes
The length of the read request must not cross the naturally aligned address boundary of the corresponding Maximum Read Request Size.
11 - - Reserved.
10:8 RW 3'b001 Peripheral Channel Address Aligned Maximum Payload Size Selected:
  • 3'b000: Reserved
  • 3'b001: 64 bytes
It must never be more than the value stated in the Peripheral Channel Maximum Payload Size Supported field.The payload of the transaction must not cross the naturally aligned address boundary of the corresponding Maximum Payload Size.
7 - - Reserved.
6:4 R - Indicates value set for Peripheral Channel Maximum Payload Size Supported parameter.
3:2 - - Reserved.
1 R 0 Peripheral Channel Ready:
  • 1: Channel is ready
  • 0: Channel is not ready
0 RW 1 Peripheral Channel Enable:
  • 1: Channel is enabled
  • 0: Channel is disabled
While you clear this bit from 1 to 0, this triggers a reset to the Peripheral Channel.
Table 38.  Channel 1 Capabilities and Configurations Register Description
Bit Access Type Default Value Description
31:22 - - Reserved.
21:16 RW 0 Operating Maximum Virtual Wire Count - The maximum number of Virtual Wire groups that can be sent in a single Virtual Wire packet. The value configured in this field must never be more than the value stated in MAX_VW_COUNT. The default value 0 indicates count of 1. Other legal values:
  • 6'b000111: 8 count
  • 6'b001000: 9 count
  • 6'b001001: 10 count
  • 6'b001010: 11 count
  • 6'b001011: 12 count
  • 6'b001100: 13 count
  • 6'b001101: 14 count
  • 6'b001110: 15 count
  • 6'b001111: 16 count
15:14 - - Reserved.
13:8 R - Indicates value set for MAX_VW_COUNT parameter.
7:2 - - Reserved.
1 R 0 Virtual Wire Channel Ready:
  • 1: Channel is ready
  • 0: Channel is not ready
0 RW 0 Virtual Wire Channel Enable:
  • 1: Channel is enabled
  • 0: Channel is disabled
When you clear this bit, it does not reset the Virtual Wire Channel. Therefore, the state of all the Virtual Wires must be maintained.