Embedded Peripherals IP User Guide

ID 683130
Date 2/09/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

6.2. Functional Description

Figure 15. System with a SPI Agent to Avalon® Host Bridge Core
Figure 16. System with a JTAG to Avalon® Host Bridge Core
Note: System clock must be at least 2X faster than the JTAG clock.

The SPI Agent to Avalon® Host Bridge and the JTAG to Avalon® Host Bridge cores accept encoded streams of bytes with transaction data on their respective physical interfaces and initiate Avalon® -MM transactions on their Avalon® -MM interfaces. Each bridge consists of the following cores, which are available as stand-alone components in Platform Designer:

  • Avalon® -ST Serial Peripheral Interface and Avalon® -ST JTAG Interface—Accepts incoming data in bits and packs them into bytes.
  • Avalon® -ST Bytes to Packets Converter—Transforms packets into encoded stream of bytes, and a likewise encoded stream of bytes into packets.
  • Avalon® -ST Packets to Transactions Converter—Transforms packets with data encoded according to a specific protocol into Avalon® -MM transactions, and encodes the responses into packets using the same protocol.
  • Avalon® -ST Single Clock FIFO—Buffers data from the Avalon® -ST JTAG Interface core. The FIFO is only used in the JTAG to Avalon® Host Bridge.

    For the bridges to successfully transform the incoming streams of bytes to Avalon® -MM transactions, the streams of bytes must be constructed according to the protocols used by the cores.

Note: When you connect the JTAG Avalon Host Bridge component to a agent that back-pressures the host interface on this component, then using the System Console master_write_from_file command may result in data loss at the host interface or hung command in System Console.
Figure 17. Bits to Avalon® -MM Transaction (Write)The following example shows how a bytestream changes as it is transferred through the different layers in the bridges for write transaction.
Figure 18. Write ResponseAfter sending a write transaction packet through MOSI bus, the host has to initiate 8 bytes of IDLE transaction on the MOSI bus in order to get the write response from the MISO bus. The following figure shows the write response transaction that constructed by the bridge in the MISO bus. The most significant bit of the command is inversed.
Figure 19. Bits to Avalon® -MM Transaction (Read)The following figure shows how a bytestream changes as it is transferred through the different layers in the bridges for a read transaction.
Figure 20. Read ResponseAfter sending a read transaction through MOSI bus, the host has to initiate IDLE transaction on the MOSI bus to get the read response from the MISO bus. There is a possibility that the Avalon agent device is yet to return the read data, therefore the bridge returns 0x4A until read data is received. When read data is received by the bridge, it sends channel byte as the first byte followed by the SOP and data byte. The following figure shows the read response transaction that constructed by the bridge in the MISO bus.