1. Generating Initial I/O Timing Data for Intel FPGAs
|Intel® Quartus® Prime Design Suite 21.3|
This document describes generating initial I/O timing data and I/O element delay information for Intel FPGA devices using the Intel® Quartus® Prime software GUI or Tcl commands.
Initial I/O timing data is useful for early pin planning and PCB design. You can generate initial timing data for the following relevant timing parameters to adjust the design timing budget when considering I/O standards and pin placement.
Input setup time (tSU)
Input hold time (tH)
tSU and tH Timing Parameters
Clock to output delay (tCO)
tCO Timing Parameters
Generating initial I/O timing information includes the following steps:
- Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device
- Step 2: Define I/O Standard and Pin Locations
- Step 3: Specify Device Operating Conditions
- Step 4: View I/O Timing in Datasheet Report
Figure 1. I/O Timing Data Generation Flow
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