AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

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ID 683103
Date 12/09/2021
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1. Generating Initial I/O Timing Data for Intel FPGAs

Updated for:
Intel® Quartus® Prime Design Suite 21.3
This document describes generating initial I/O timing data and I/O element delay information for Intel FPGA devices using the Intel® Quartus® Prime software GUI or Tcl commands.

Initial I/O timing data is useful for early pin planning and PCB design. You can generate initial timing data for the following relevant timing parameters to adjust the design timing budget when considering I/O standards and pin placement.

I/O Timing Parameters
Timing Parameter Description

Input setup time (tSU)

Input hold time (tH)

tSU and tH Timing Parameters
tSU = 
input pin to input register data delay 
+ input register micro setup time 
- input pin to input register clock delay
tH = 
- input pin to input register data delay 
+ input register micro hold time 
+ input pin to input register clock delay

Clock to output delay (tCO)

tCO Timing Parameters
tCO = 
+ clock pad to output register delay 
+ output register clock-to-output delay 
+ output register to output pin delay

Generating initial I/O timing information includes the following steps:

Figure 1. I/O Timing Data Generation Flow

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