AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021

2.1. Step 1: Create Simple Flip-Flop Design

Follow these steps to define and synthesize the flip-flop logic to generate the IOE:
  1. Create a new project in Intel® Quartus® Prime Pro Edition software version 21.3.
  2. Click Assignments > Device, specify your target device Family and a Target device. For example, select the AGFA014R24A Intel® Agilex™ FPGA.
  3. Click File > New and create a Block Diagram/Schematic File.
  4. To add components to the schematic, click the Symbol Tool button.
    Figure 11. Symbol Tool Button in Block Editor
  5. Under Name, type DFF, and then click OK. Click twice in the Block Editor to insert two instances of the DFF symbol.
  6. Repeat 4 through 5 to add an input input pin, clock input pin, and output_1 output pin.
  7. Connect the pins to the DFFs using the Orthogonal Node Tool button, and draw wire lines between the pins and DFFs symbols, as Figure 12 shows.
    Figure 12. DFFs with Pin Connections
  8. To synthesize the DFFs, click Processing > Start > Start Analysis & Synthesis. Synthesis generates the minimum design netlist required to obtain I/O timing Data.

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