AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021
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2.2. Step 2: Define I/O Delay Chain and Clock Settings

The I/O delay chain setting that you specify determines the minimum and maximum delay path from input pin to output pin through each register. specifies the range of I/O delay chain settings for this example.
Table 1.  I/O Delay Chain Settings for Example
Setting Maximum Value Minimum Value
Input Delay Chain 63 0
Output Delay Chain 15 0

To assign the I/O delay chain settings, follow these steps:

  1. Click Assignments > Assignment Editor.
  2. In the Assignment Editor, assign settings to registers and pins, according to your design specifications, as the following example assignments show:
    Figure 13. Registers and Pins in Assignment Editor
  3. To compile the design, click Processing > Start Compilation. The Compiler implements the assignments during compilation, and then launches the Timing Analyzer automatically.

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