2. Generating I/O Element Delay Information for Intel FPGAs
You can specify a different input delay for pin in your design from the pin-to-input register, or a delay from the output register-to-output pin values. This capability allows you to ensure that the signals within a bus have the same delay going into or out of the device. For detailed descriptions of the various IOE structures in different FPGA devices, refer to the FPGA device documentation in related links.
Generating IOE delay information includes the following steps in the flow:
- Step 1: Create Simple Flip-Flop Design
- Step 2: Define I/O Delay Chain and Clock Settings
- Step 3: Specify Device Operating Conditions
- Step 4: View IOE Timing Delay with Report Path
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