AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021

1.3. Step 3: Specify Device Operating Conditions

Follow these steps to set operating conditions for timing analysis following full compilation.
  1. The Timing Analyzer launches automatically and updates the timing netlist following full compilation, as Step 2: Define I/O Standard and Pin Locations describes.
  2. Under Set Operating Conditions, select one or more of the available timing models, such as Slow vid3 100C Model and Fast vid3 100C Model.
    Figure 5. Set Operating Conditions Pane