AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021
Public
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2.4.1. Example 1: Viewing the Input Element Delay in Reports

In the following example, Report Path shows the maximum delay of input pin to register for the Slow mode at 0C Model operating condition.

Figure 17. Input Element Delay (Input Delay Chain Setting = 0)

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