AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

Download PDF
ID 683103
Date 12/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. Generating Initial I/O Timing Data for Intel FPGAs 2. Generating I/O Element Delay Information for Intel FPGAs
1. Generating Initial I/O Timing Data for Intel FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation
2. Generating I/O Element Delay Information for Intel FPGAs x
2.1. Step 1: Create Simple Flip-Flop Design 2.2. Step 2: Define I/O Delay Chain and Clock Settings 2.3. Step 3: Specify Device Operating Conditions 2.4. Step 4: View IOE Timing Delay with Report Path 2.5. Scripted IOE Information Generation 2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs
2.4. Step 4: View IOE Timing Delay with Report Path x
2.4.1. Example 1: Viewing the Input Element Delay in Reports 2.4.2. Example 2: Viewing the Output Element Delay in Reports
1. Generating Initial I/O Timing Data for Intel FPGAs
2. Generating I/O Element Delay Information for Intel FPGAs

2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

Document Version Intel® Quartus® Prime Version Changes
2021.12.09 21.3
  • Retitled document to encompass new chapter on IOE timing information.
  • Revised Generating Initial I/O Timing Data for Intel FPGAs topic to include IOE timing information.
  • Updated Step 2: Define I/O Standard and Pin Locations topic for automatic launch of Timing Analyzer following full compilation.
  • Updated Step 3: Specify Device Operating Conditions topic for automatic launch of Timing Analyzer following full compilation.
  • Added new chapter: Generating I/O Element Delay Information for Intel FPGAs.
2019.12.08 19.3
  • Revised title to reflect content.
  • Added support for Intel® Stratix® 10 and Intel® Agilex™ FPGAs.
  • Added step numbers to flow.
  • Added timing parameter diagrams.
  • Updated screenshots to reflect latest version.
  • Updated links to related documents.
  • Applied latest product naming and style conventions.
2016.10.31 16.1
  • First public release.
Level Two Title