AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021
Public
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2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

Document Version Intel® Quartus® Prime Version Changes
2021.12.09 21.3
  • Retitled document to encompass new chapter on IOE timing information.
  • Revised Generating Initial I/O Timing Data for Intel FPGAs topic to include IOE timing information.
  • Updated Step 2: Define I/O Standard and Pin Locations topic for automatic launch of Timing Analyzer following full compilation.
  • Updated Step 3: Specify Device Operating Conditions topic for automatic launch of Timing Analyzer following full compilation.
  • Added new chapter: Generating I/O Element Delay Information for Intel FPGAs.
2019.12.08 19.3
  • Revised title to reflect content.
  • Added support for Intel® Stratix® 10 and Intel® Agilex™ FPGAs.
  • Added step numbers to flow.
  • Added timing parameter diagrams.
  • Updated screenshots to reflect latest version.
  • Updated links to related documents.
  • Applied latest product naming and style conventions.
2016.10.31 16.1
  • First public release.

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