AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021
Public
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1.2. Step 2: Define I/O Standard and Pin Locations

The specific pin locations and I/O standard you assign to the device pins impacts the timing parameter values. Follow these steps to assign the pin I/O standard and location constraints:
  1. Click Assignments > Pin Planner.
  2. Assign pin location and I/O standard constraints according to your design specifications. Enter the Node Name, Direction, Location, and I/O Standard values for the pins in the design in the All Pins spreadsheet. Alternatively, drag node names into the Pin Planner package view.
    Figure 4. Pin Locations and I/O Standards Assignments in Pin Planner
  3. To compile the design, click Processing > Start Compilation. The Compiler generates I/O timing information during full compilation, and automatically launches the Timing Analyzer with updated netlist at the end of full compilation.

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