AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

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ID 683103
Date 12/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. Generating Initial I/O Timing Data for Intel FPGAs 2. Generating I/O Element Delay Information for Intel FPGAs
1. Generating Initial I/O Timing Data for Intel FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation
2. Generating I/O Element Delay Information for Intel FPGAs x
2.1. Step 1: Create Simple Flip-Flop Design 2.2. Step 2: Define I/O Delay Chain and Clock Settings 2.3. Step 3: Specify Device Operating Conditions 2.4. Step 4: View IOE Timing Delay with Report Path 2.5. Scripted IOE Information Generation 2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs
2.4. Step 4: View IOE Timing Delay with Report Path x
2.4.1. Example 1: Viewing the Input Element Delay in Reports 2.4.2. Example 2: Viewing the Output Element Delay in Reports
1. Generating Initial I/O Timing Data for Intel FPGAs
2. Generating I/O Element Delay Information for Intel FPGAs

1.2. Step 2: Define I/O Standard and Pin Locations

The specific pin locations and I/O standard you assign to the device pins impacts the timing parameter values. Follow these steps to assign the pin I/O standard and location constraints:
  1. Click Assignments > Pin Planner.
  2. Assign pin location and I/O standard constraints according to your design specifications. Enter the Node Name, Direction, Location, and I/O Standard values for the pins in the design in the All Pins spreadsheet. Alternatively, drag node names into the Pin Planner package view.
    Figure 4. Pin Locations and I/O Standards Assignments in Pin Planner
  3. To compile the design, click Processing > Start Compilation. The Compiler generates I/O timing information during full compilation, and automatically launches the Timing Analyzer with updated netlist at the end of full compilation.
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