AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021

2.5. Scripted IOE Information Generation

As an alternative to the using the GUI, you can create and execute a Tcl script to generate IOE timing information for your target device reflecting different delay values.
You can optionally download example scripts that are available for Intel FPGA devices from the Intel FPGA Design Store.
Note: The scripted method is available only for the Intel® Quartus® Prime software on Linux* platforms.

Follow these steps to use scripting to generate IOE information for FPGA devices reflecting these different delay values:

  • Delay from input pin to input register
  • Delay from output register to output pin.
  1. Download the following example example design Intel® Quartus® Prime project archive:
  2. In the Intel® Quartus® Prime software, click Project > Restore Archived Project and restore the gclk_21_3_0_170.qar project.
    Figure 19. Restore Archived Project
  3. To run the ioe_<device>_d1_d5.tcl script with the Timing Analyzer, run the following command:
    quartus_sta -t ioe_<device>_d1_d5.tcl
  4. Once the script completes, open the /timing_files/.txt file in a text editor. This file contains the IOE timing information.

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