2.5. Scripted IOE Information Generation
Follow these steps to use scripting to generate IOE information for FPGA devices reflecting these different delay values:
- Delay from input pin to input register
- Delay from output register to output pin.
- Download the following example example design Intel® Quartus® Prime project archive:
- In the Intel® Quartus® Prime software, click and restore the gclk_21_3_0_170.qar project.
Figure 19. Restore Archived Project
- To run the ioe_<device>_d1_d5.tcl script with the Timing Analyzer, run the following command:
quartus_sta -t ioe_<device>_d1_d5.tcl
- Once the script completes, open the /timing_files/.txt file in a text editor. This file contains the IOE timing information.
Did you find the information on this page useful?