AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

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ID 683103
Date 12/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. Generating Initial I/O Timing Data for Intel FPGAs 2. Generating I/O Element Delay Information for Intel FPGAs
1. Generating Initial I/O Timing Data for Intel FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation
2. Generating I/O Element Delay Information for Intel FPGAs x
2.1. Step 1: Create Simple Flip-Flop Design 2.2. Step 2: Define I/O Delay Chain and Clock Settings 2.3. Step 3: Specify Device Operating Conditions 2.4. Step 4: View IOE Timing Delay with Report Path 2.5. Scripted IOE Information Generation 2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs
2.4. Step 4: View IOE Timing Delay with Report Path x
2.4.1. Example 1: Viewing the Input Element Delay in Reports 2.4.2. Example 2: Viewing the Output Element Delay in Reports
1. Generating Initial I/O Timing Data for Intel FPGAs
2. Generating I/O Element Delay Information for Intel FPGAs

2.5. Scripted IOE Information Generation

As an alternative to the using the GUI, you can create and execute a Tcl script to generate IOE timing information for your target device reflecting different delay values.
You can optionally download example scripts that are available for Intel FPGA devices from the Intel FPGA Design Store.
Note: The scripted method is available only for the Intel® Quartus® Prime software on Linux* platforms.

Follow these steps to use scripting to generate IOE information for FPGA devices reflecting these different delay values:

  • Delay from input pin to input register
  • Delay from output register to output pin.
  1. Download the following example example design Intel® Quartus® Prime project archive:
    gclk_21_3_0_170.qar
  2. In the Intel® Quartus® Prime software, click Project > Restore Archived Project and restore the gclk_21_3_0_170.qar project.
    Figure 19. Restore Archived Project
  3. To run the ioe_<device>_d1_d5.tcl script with the Timing Analyzer, run the following command: 
    quartus_sta -t ioe_<device>_d1_d5.tcl
  4. Once the script completes, open the /timing_files/.txt file in a text editor. This file contains the IOE timing information.
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