AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021

2.4.2. Example 2: Viewing the Output Element Delay in Reports

In the following example, Report Path shows the maximum delay of register to output pin for the Slow mode at 0C Model operating condition.

Figure 18. Output Element Delay (Input Delay Chain Setting = 0)

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