1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device
Follow these steps to define and synthesize the minimum flip-flop logic to generate initial I/O timing data:
- Create a new project in Intel® Quartus® Prime Pro Edition software version 19.3.
- Click Family and a Target device. For example, select the AGFA014R24 Intel® Agilex™ FPGA. , specify your target device
- Click Block Diagram/Schematic File. and create a
- To add components to the schematic, click the Symbol Tool button.
Figure 2. Insert Pins and Wires in Block Editor
- Under Name, type DFF, and then click OK. Click in the Block Editor to insert the DFF symbol.
- Repeat 4 through 5 to add an Input_data input pin, Clock input pin, and Output_data output pin.
- To connect the pins to the DFF, click the Orthogonal Node Tool button, and then draw wire lines between the pin and DFF symbol.
Figure 3. DFF with Pin Connections
- To synthesize the DFF, click . Synthesis generates the minimum design netlist required to obtain I/O timing Data.
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