AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

ID 683103
Date 12/09/2021

1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device

Follow these steps to define and synthesize the minimum flip-flop logic to generate initial I/O timing data:
  1. Create a new project in Intel® Quartus® Prime Pro Edition software version 19.3.
  2. Click Assignments > Device, specify your target device Family and a Target device. For example, select the AGFA014R24 Intel® Agilex™ FPGA.
  3. Click File > New and create a Block Diagram/Schematic File.
  4. To add components to the schematic, click the Symbol Tool button.
    Figure 2. Insert Pins and Wires in Block Editor
  5. Under Name, type DFF, and then click OK. Click in the Block Editor to insert the DFF symbol.
  6. Repeat 4 through 5 to add an Input_data input pin, Clock input pin, and Output_data output pin.
  7. To connect the pins to the DFF, click the Orthogonal Node Tool button, and then draw wire lines between the pin and DFF symbol.
    Figure 3. DFF with Pin Connections
  8. To synthesize the DFF, click Processing > Start > Start Analysis & Synthesis. Synthesis generates the minimum design netlist required to obtain I/O timing Data.