AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs

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ID 683103
Date 12/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. Generating Initial I/O Timing Data for Intel FPGAs 2. Generating I/O Element Delay Information for Intel FPGAs
1. Generating Initial I/O Timing Data for Intel FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation
2. Generating I/O Element Delay Information for Intel FPGAs x
2.1. Step 1: Create Simple Flip-Flop Design 2.2. Step 2: Define I/O Delay Chain and Clock Settings 2.3. Step 3: Specify Device Operating Conditions 2.4. Step 4: View IOE Timing Delay with Report Path 2.5. Scripted IOE Information Generation 2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs
2.4. Step 4: View IOE Timing Delay with Report Path x
2.4.1. Example 1: Viewing the Input Element Delay in Reports 2.4.2. Example 2: Viewing the Output Element Delay in Reports
1. Generating Initial I/O Timing Data for Intel FPGAs
2. Generating I/O Element Delay Information for Intel FPGAs

1.5. Scripted I/O Timing Data Generation

You can use a Tcl script to generate I/O timing information with or without using the Intel® Quartus® Prime software user interface.
The scripted approach generates text-based I/O timing parameter data for supported I/O standards.
Note: The scripted method is available only for Linux* platforms.

Follow these steps to generate I/O timing information reflecting multiple I/O standards for Intel® Agilex™ , Intel® Stratix® 10, and Intel® Arria® 10 devices:

  1. Download the appropriate Intel® Quartus® Prime project archive file for your target device family:
  2. To restore the .qar project archive, launch the Intel® Quartus® Prime Pro Edition software and click Project > Restore Archived Project. Alternatively, run the following command line equivalent without launching the GUI: 
    quartus_sh --restore <archive file>
    The io_timing_<device>_restored directory now contains the qdb subfolder and various files.
  3. To run the script with the Intel® Quartus® Prime Timing Analyzer, run the following command: 
    quartus_sta –t <device>.tcl
    Wait for completion. The script execution may require 8 hours or more because each change on I/O standard or pin location requires design recompilation.
  4. To view the timing parameter values, open the generated text files in timing_files, with names such as timing_tsuthtco_<device>_<speed>_<IO_standard>.txt.
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