AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Altera FPGAs

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ID 683103
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Generating Initial I/O Timing Data for Altera FPGAs 2. Generating I/O Element Delay Information for Altera FPGAs
1. Generating Initial I/O Timing Data for Altera FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Altera FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation
2. Generating I/O Element Delay Information for Altera FPGAs x
2.1. Step 1: Create Simple Flip-Flop Design 2.2. Step 2: Define I/O Delay Chain and Clock Settings 2.3. Step 3: Specify Device Operating Conditions 2.4. Step 4: View IOE Timing Delay with Report Path 2.5. Scripted IOE Information Generation 2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Altera FPGAs
2.4. Step 4: View IOE Timing Delay with Report Path x
2.4.1. Example 1: Viewing the Input Element Delay in Reports 2.4.2. Example 2: Viewing the Output Element Delay in Reports
1. Generating Initial I/O Timing Data for Altera FPGAs
2. Generating I/O Element Delay Information for Altera FPGAs

2.1. Step 1: Create Simple Flip-Flop Design

Follow these steps to define and synthesize the flip-flop logic to generate the IOE:
  1. Create a new project in Quartus® Prime Pro Edition software version 25.3.
  2. Click Assignments > Device, specify your target device Family and a Target device. For example, select the AGFA014R24A Agilex™ FPGA portfolio FPGA.
  3. Click File > New click Verilog HDL File.
  4. Create a simple flip-flop design, as the following shows: 
    module dff (
     input D, 
     input clock,
     output reg Q);
     always @ (posedge clock)
     begin
     Q <= D;
     end
endmodule
  5. Repeat step 3 to create the flip-flop design that connects two instances of the DFF, as the following shows: 
    module design_1(
     input	clock,
     input	input_1,
     output output_1);
dff register_in (.clock(clock),.D(input_1), .Q(Q));
dff register_out (.clock(clock),.D(Q), .Q(output_1));
endmodule
    Figure 10. DFFs with Pin Connection


  6. To synthesize the DFF, click Processing > Start > Start Analysis & Synthesis. Synthesis generates the minimum design netlist required to obtain I/O timing data.
Level Two Title