AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Altera FPGAs

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ID 683103
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Generating Initial I/O Timing Data for Altera FPGAs 2. Generating I/O Element Delay Information for Altera FPGAs
1. Generating Initial I/O Timing Data for Altera FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Altera FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation
2. Generating I/O Element Delay Information for Altera FPGAs x
2.1. Step 1: Create Simple Flip-Flop Design 2.2. Step 2: Define I/O Delay Chain and Clock Settings 2.3. Step 3: Specify Device Operating Conditions 2.4. Step 4: View IOE Timing Delay with Report Path 2.5. Scripted IOE Information Generation 2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Altera FPGAs
2.4. Step 4: View IOE Timing Delay with Report Path x
2.4.1. Example 1: Viewing the Input Element Delay in Reports 2.4.2. Example 2: Viewing the Output Element Delay in Reports
1. Generating Initial I/O Timing Data for Altera FPGAs
2. Generating I/O Element Delay Information for Altera FPGAs

2.3. Step 3: Specify Device Operating Conditions

Follow these steps to set operating conditions in the Timing Analyzer after compilation:
  • Under Set Operating Conditions, enable or disable one or more operating condition timing models:
    Figure 12. Set Operating Conditions Pane
  • In the Tasks pane, click Set Operating Conditions. Specify the desired operating conditions in the Set Operating Conditions dialog box.
Figure 13. Set Operating Conditions Dialog Box
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