AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Altera FPGAs
ID
683103
Date
9/29/2025
Public
1. Generating Initial I/O Timing Data for Altera FPGAs
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 25.3 |
This document describes generating initial I/O timing data and I/O element delay information for Altera FPGA devices using the Quartus® Prime software GUI or Tcl commands.
Initial I/O timing data is useful for early pin planning and PCB design. You can generate initial timing data for the following relevant timing parameters to adjust the design timing budget when considering I/O standards and pin placement.
| Timing Parameter | Description |
|---|---|
Input setup time (tSU) Input hold time (tH) |
tSU and tH Timing Parameters
tSU = input pin to input register data delay + input register micro setup time - input pin to input register clock delay tH = - input pin to input register data delay + input register micro hold time + input pin to input register clock delay |
Clock to output delay (tCO) |
tCO Timing Parameters
tCO = + clock pad to output register delay + output register clock-to-output delay + output register to output pin delay |
Generating initial I/O timing information includes the following steps:
- Step 1: Synthesize a Flip-flop for the Target Altera FPGA Device
- Step 2: Define I/O Standard and Pin Locations
- Step 3: Specify Device Operating Conditions
- Step 4: View I/O Timing in Datasheet Report
Figure 1. I/O Timing Data Generation Flow