AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

ID 683075
Date 8/09/2019
Public
Document Table of Contents

1.4. Error Injection

To test the error detection block, you can intentionally inject errors. This error injection methodology provides design verification and system fault tolerance characterization. Using the EDERROR_INJECT JTAG instruction, you can inject a single error, double errors, or double-adjacent errors to the configuration memory.

The EDERROR_INJECT JTAG instructions is not designed to test internal scrubbing. If you want to validate the internal scrubbing feature, Intel recommends that you use the Intel® Quartus® Prime Fault Injection Debugger.

Table 6.   EDERROR_INJECT JTAG Instruction
JTAG Instruction Instruction Code Description
EDERROR_INJECT 00 0001 0101 This instruction controls the 21-bit JTAG fault injection register that is used for error injection.
Note: For Stratix® V III devices, you can only execute the EDERROR_INJECT JTAG instruction at a 50 MHz error detection frequency. Refer to the related information.