AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

ID 683075
Date 8/09/2019
Document Table of Contents

1.1.4. Error Message Register

The EMR contains information on the error type, the location of the error, and the actual syndrome. This register is 46 bits wide in Arria® II, Stratix® III, and Stratix® IV devices; 67 bits wide in Arria® V, Cyclone® V, and Stratix® V devices. Table 2 and Table 3 list the types of errors and locations reported. The EMR does not identify the location bits for other types of errors.

The location of the errors consist of the column frame number, byte location within the frame, and bit location in the byte. You can shift out the contents of the register through the SHIFT_EDERROR_REG JTAG instruction or to the core through the core interface.

Table 1.  SHIFT_EDERROR_REG JTAG Instruction
JTAG Instruction Instruction Code Description
SHIFT_EDERROR_REG 00 0001 0111 The JTAG instruction connects the EMR to the JTAG pin in the error detection block between the TDI and TDO pins.

The contents of the EMR is updated when an error or errors occur. You must transfer the contents of the EMR out before they are overwritten by the next error message. The minimum interval time between two EMR updates is different for every device. For more information about the minimum update interval of the EMR, see related information below.

Note: You can slow down the error detection process to have sufficient time to read out the EMR by controlling the error detection frequency.