AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

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ID 683075
Date 8/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices x
1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1.1. Functional Description x
1.1.1. Configuration Error Detection 1.1.2. User Mode Error Detection 1.1.3. Error Detection Pin 1.1.4. Error Message Register 1.1.5. Error Detection Timing
1.1.4. Error Message Register x
1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices 1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices
1.3. Using the Error Detection CRC Feature x
1.3.1. Error Detection using User Logic 1.3.2. Error Detection using an External Host
1.3.1. Error Detection using User Logic x
1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal 1.3.1.2. Unloading the EMR through User Logic 1.3.1.3. Accessing the Error Detection Block through User Logic 1.3.1.4. User Logic Control Block 1.3.1.5. User Logic Control Block Signals
1.3.2. Error Detection using an External Host x
1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal 1.3.2.2. Unloading the EMR using an External Host
1.4. Error Injection x
1.4.1. Fault Injection Register 1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction 1.4.3. Clearing Fault Injection Register
1.4.1. Fault Injection Register x
1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices
1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction x
1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV 1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.1.4. Error Message Register

The EMR contains information on the error type, the location of the error, and the actual syndrome. This register is 46 bits wide in Arria® II, Stratix® III, and Stratix® IV devices; 67 bits wide in Arria® V, Cyclone® V, and Stratix® V devices. Table 2 and Table 3 list the types of errors and locations reported. The EMR does not identify the location bits for other types of errors.

The location of the errors consist of the column frame number, byte location within the frame, and bit location in the byte. You can shift out the contents of the register through the SHIFT_EDERROR_REG JTAG instruction or to the core through the core interface.

Table 1.  SHIFT_EDERROR_REG JTAG Instruction
JTAG Instruction Instruction Code Description
SHIFT_EDERROR_REG 00 0001 0111 The JTAG instruction connects the EMR to the JTAG pin in the error detection block between the TDI and TDO pins.

The contents of the EMR is updated when an error or errors occur. You must transfer the contents of the EMR out before they are overwritten by the next error message. The minimum interval time between two EMR updates is different for every device. For more information about the minimum update interval of the EMR, see related information below.

Note: You can slow down the error detection process to have sufficient time to read out the EMR by controlling the error detection frequency.

Section Content
EMR for Arria II, Stratix III, and Stratix IV Devices
EMR for Arria V, Cyclone V, and Stratix V Devices

Related Information
Level Two Title