AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

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ID 683075
Date 8/09/2019
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Document Table of Contents
Document Table of Contents x
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices x
1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1.1. Functional Description x
1.1.1. Configuration Error Detection 1.1.2. User Mode Error Detection 1.1.3. Error Detection Pin 1.1.4. Error Message Register 1.1.5. Error Detection Timing
1.1.4. Error Message Register x
1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices 1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices
1.3. Using the Error Detection CRC Feature x
1.3.1. Error Detection using User Logic 1.3.2. Error Detection using an External Host
1.3.1. Error Detection using User Logic x
1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal 1.3.1.2. Unloading the EMR through User Logic 1.3.1.3. Accessing the Error Detection Block through User Logic Example of the Input and Output Ports of a WYSIWYG Atom in a Stratix® III Device 1.3.1.4. User Logic Control Block 1.3.1.5. User Logic Control Block Signals
1.3.2. Error Detection using an External Host x
1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal 1.3.2.2. Unloading the EMR using an External Host
1.4. Error Injection x
1.4.1. Fault Injection Register 1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction 1.4.3. Clearing Fault Injection Register
1.4.1. Fault Injection Register x
1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices
1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction x
1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV 1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.3.1.3. Accessing the Error Detection Block through User Logic

Use the <device>_crcblock WYSIWYG component to establish the interface from the user logic to the error detection circuit. The <device>_crcblock primitive atom contains the input and output ports that you must include in the atom. To access the logic array, insert the <device>_crcblock WYSIWYG atom into your design.

You cannot use the information provided by the EMR to detect soft errors. Instead, use the information provided by the CRC_ERROR output signal because it is not affected by soft errors.

Figure 8. User Logic Error Detection Block DiagramFigure shows the error detection feature and the WYSIWYG atom that you must enable in your design.
Note: For the Intel® Quartus® Prime software version 8.0 SP1 or earlier, you must enable the error detection CRC feature in the Device & Pin Options dialog box in the Intel® Quartus® Prime software when you include the <device>_crcblock WYSIWYG atom in your design.

To enable the <device>_crcblock WYSIWYG atom, name the atom for each device accordingly. For example, the WYSIWYG atom for the Stratix® III device is stratixiii_crcblock and the Arria® II device is arriaii_crcblock.

Table 4.  CRC Block Input and Output PortsTable lists the input and output ports that you must include in the WYSIWYG atom.
Port Input/Output Definition
<crcblock_name> Input Unique identifier for the CRC block and represents any identifier name that is legal for the given description language, such as the Verilog HDL, VHDL, and Altera Hardware Description Language (AHDL). This is a required field.
.clk(<clock source>) Input Designates the clock input of this cell. All operations of this cell are with respect to the rising edge of the clock. Whether loading data into the cell or out of the cell, this always occurs on the rising edge. This is a required port.
.shiftnld (<shiftnld source>) Input
  • An input into the error detection block.
  • If shiftnld=1, the user shift register shifts the data to the regout port at each rising edge of the clk port.
  • If shiftnld=0, the user shift register parallel loads the contents of the user update register. This is a required port.
  • This input triggers clock enable for the user update register to de-assert after two EDCLK cycles. After driving the ED_SHIFTNLD signal low, wait at least two EDCLK cycles before clocking the ED_CLK signal.
.crcerror (<crcerror out destination>) Output
  • Output of the cell that is synchronized to the internal oscillator of the device (100-MHz or 80-MHz internal oscillator) and not to the clk port. This output asserts automatically high if the error block detects that a SRAM bit has flipped and the internal CRC computation has shown a difference with respect to the pre-computed value.
  • Connect this signal to an output pin or a bidirectional pin. If you connect this output signal to an output pin, you can only monitor the CRC_ERROR pin (the core logic cannot access this output). If the core logic uses the CRC_ERROR signal to read the error detection logic, connect this signal to a BIDIR pin. The signal is fed to the core indirectly by feeding a BIDIR pin that has its output enable port (oe) connected to VCC.
  • The signal that is routed to the CRC_ERROR pin is also routed to the core.
.regout(<output destination>) Output
  • Output of the user shift register synchronized to the clk port, to be read by the core logic.
  • This shifts one bit at each cycle and follows the LSB-first format.

Example of the Input and Output Ports of a WYSIWYG Atom in a Stratix® III Device

Example shows the input and output ports of a WYSIWYG atom in a Stratix® III device. 
stratixiii_crcblock <crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>)
);
defparam crc_wysiwyg_atom.oscillator_divider = 2
Note: The crc_wysiwyg_atom.oscillator_divider parameter describes the clock divider for the error detection frequency of the <device>_crcblock WYSIWYG atom.
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