AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

ID 683075
Date 8/09/2019
Document Table of Contents

1.1.2. User Mode Error Detection

During user mode, the contents of a configured CRAM bit may be affected by soft errors. User mode error detection allows you to determine the type of soft error and to identify the location of the affected bit.

After the configuration cycle is complete, the error detection feature computes the CRC value of the configured CRAM bits and compares the results with the pre-computed CRC value. If both the CRC values match, the resulting CRC signature is set to 0 to indicate that no error was detected. The error detection process continues until the device is reset by setting nCONFIG low.

If CRC errors occur, the resulting signature is non-zero and the CRC_ERROR pin is set high to flag an error. When errors occur, the search engine in the error detection state machine identifies the error type and error location. All types of CRC errors can be detected in a frame. The results of the search engine are stored in the EMR. You can shift out the contents of this register through the JTAG instruction or core interface logics. You can shift out the contents while the error detection block is running.