AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

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ID 683075
Date 8/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices x
1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1.1. Functional Description x
1.1.1. Configuration Error Detection 1.1.2. User Mode Error Detection 1.1.3. Error Detection Pin 1.1.4. Error Message Register 1.1.5. Error Detection Timing
1.1.4. Error Message Register x
1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices 1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices
1.3. Using the Error Detection CRC Feature x
1.3.1. Error Detection using User Logic 1.3.2. Error Detection using an External Host
1.3.1. Error Detection using User Logic x
1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal 1.3.1.2. Unloading the EMR through User Logic 1.3.1.3. Accessing the Error Detection Block through User Logic 1.3.1.4. User Logic Control Block 1.3.1.5. User Logic Control Block Signals
1.3.2. Error Detection using an External Host x
1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal 1.3.2.2. Unloading the EMR using an External Host
1.4. Error Injection x
1.4.1. Fault Injection Register 1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction 1.4.3. Clearing Fault Injection Register
1.4.1. Fault Injection Register x
1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices
1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction x
1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV 1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

Document Version Changes
2019.08.09
  • Updated the topic about error injection to specify that EDERROR_INJECT is not designed to test the internal scrubbing feature. Use the Fault Injection Debugger instead.
  • Updated the topic abouit clearing the fault injection register to specify that the previous example codes are for Arria® II, Stratix® III, and Stratix® IV devices, and add example codes for Arria® V, Stratix® V, and Cyclone® V devices.
  • Added steps to modify .jam file for use in a multi-device JTAG chain.
  • Added steps to execute .jam file using quartus_jli command.
2018.05.07
  • Rebranded to Intel.
  • Updated Examples:
    • Example of .jam File to Inject Single-Bit Error for Arria II, Stratix III, and Stratix IV Devices
    • Example of .jam File to Inject Single-Bit Error for Arria V, Cyclone V, and Stratix V Devices
    • Example of .jam File to Clear the Contents of the Fault Injection Register
Date Version Changes
June 2017 2017.06.14 Corrected Example 5.
August 2016 2016.08.03
  • Corrected Fault Injection Register sub-section title.
August 2015 2015.08.20
  • Fixed editorial error in Fault Injection Register.
  • Fixed Related links descriptions.
  • Removed link to an application note for mature products, AN357.
May 2015 2015.05.04
  • Updated Example of .jam File to Inject Single-Bit Error for Arria V, Cyclone V and Stratix V Devices by correcting double quotation type and added semicolon in line 35.
  • Template update.
December 2014 2014.12.15
  • Updated Figure 3 on page 5.
April 2014 3.0
  • Updated Table 5 on page 11 to correct the .clk(<clock source>) port operation from falling edge to rising edge of the clock.
  • Updated document to support Arria V and Cyclone V.
  • Updated Figure 3 on page 5.
  • Added Example 3 on page 16.
June 2011 2.0
  • Added Figure 3, Figure 10, and Figure 12.
  • Added Table 4 and Table 9.
  • Added Example 5.
  • Added the “Error Correction” section.
  • Updated Figure 1, Figure 2, Figure 9, and Figure 11.
  • Updated Table 1, Table 3, and Table 8.
  • Updated the “Functional Description”, “Configuration Error Detection”, “User Mode Error Detection”, “Error Message Register”, “Fault Injection Register”, and “Error Injection using the EDERROR_INJECT JTAG Instruction” sections.
  • Minor text edits.
April 2009 1.1
  • Updated the “Introduction”, “Error Injection using EDERROR_INJECT JTAG Instruction”, “Error Injection”, and “Error Detection Pin” sections.
  • Updated Table 4 and Table 8.
December 2008 1.0 Initial release.
Level Two Title