AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

ID 683075
Date 8/09/2019
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1.1.1. Configuration Error Detection

When the Intel® Quartus® Prime software generates the configuration bitstream, it also computes a CRC value for each data frame. The number of data frames and the length of the frames in a configuration bitstream vary in each device. Therefore, a configuration bitstream can contain more than one CRC values depending on the number of data frames in the bitstream.

When a data frame is loaded into the FPGA during configuration, the pre-computed CRC value shifts into the CRC circuitry in the FPGA. At the same time, the CRC engine in the FPGA computes the CRC value for the data frame received, and stores the CRC value into the configuration RAM (CRAM). The pre-computed CRC value is compared against the CRC value computed by the CRC engine. If the CRC values do not match, nSTATUS is set low to flag a configuration error.

You can test the capability of the configuration error detection feature by either modifying the configuration bitstream or intentionally corrupting the configuration bitstream during configuration.