AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

ID 683075
Date 8/09/2019
Document Table of Contents

1.1.5. Error Detection Timing

The CRC_ERROR pin is always set low during CRC signature calculation for a minimum of 32 clock cycles. When errors occur, the CRC_ERROR pin is set high after the EMR has been updated, or after 32 cycles, whichever comes last. Therefore, you can start to unload the contents of the EMR at the rising edge of the CRC_ERROR pin. At the end of this cycle, the CRC_ERROR pin is set low again for a minimum of 32 clock cycles. If the next frame also contains error, the CRC_ERROR pin pulls high again and the EMR is updated with the new error information.

Figure 4. Example of the CRC_ERROR Pin BehaviorExample of how the CRC_ERROR pin behaves when an error occurs in a data frame.

You can control the speed of the error detection process by setting the division factor of the clock frequency in the Intel® Quartus® Prime software. The divisor is a power of two, in which n is between one and eight. The divisor ranges from two through 256.

Figure 5. Error Detection Frequency Equation