1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
22.214.171.124. Unloading the EMR through User Logic
To unload the EMR through user logic, establish an interface between the user logic and the error detection circuit using the WYSIWYG atom. The WYSIWYG atom provides access to the error detection block. In addition, you must design a user logic control block to control the necessary control signals to access the WYSIWYG atom.
Figure 7. Interface Between the User Logic Control Block and the WYSIWYG Atom
Note: WYSIWYG is a technique that performs optimization on the Verilog Quartus Mapping netlist within the Intel® Quartus® Prime software.
Did you find the information on this page useful?