AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

ID 683075
Date 8/09/2019
Document Table of Contents Unloading the EMR through User Logic

To unload the EMR through user logic, establish an interface between the user logic and the error detection circuit using the WYSIWYG atom. The WYSIWYG atom provides access to the error detection block. In addition, you must design a user logic control block to control the necessary control signals to access the WYSIWYG atom.

Figure 7. Interface Between the User Logic Control Block and the WYSIWYG Atom
Note: WYSIWYG is a technique that performs optimization on the Verilog Quartus Mapping netlist within the Intel® Quartus® Prime software.

Did you find the information on this page useful?

Characters remaining:

Feedback Message