P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
Public
Document Table of Contents
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E.5. Compile and Simulate

You can run simulations in batch mode.

In batch mode, the VCS script compiles the design and runs the simulation until $finish(). Run the following command under the <example design folder>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs folder.

% sh ./vcs_setup.sh USER_DEFINED_SIM_OPTIONS=””

Setting USER_DEFINED_SIM_OPTIONS to an empty string overrides the default USER_DEFINED_SIM_OPTIONS and allows the simulation to run until $finish().