P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

1.5. Performance and Resource Utilization

The following table shows the recommended FPGA fabric speed grades for all the configurations that the Avalon® -ST IP core supports.

Table 6.   Intel® Stratix® 10 DX / Intel Agilex® 7 Recommended FPGA Fabric Speed Grades for All Avalon-ST Widths and FrequenciesThe recommended FPGA fabric speed grades are for production parts.

Lane Rate

Link Width

Application Interface Data Width

Application Clock Frequency (MHz)

Recommended FPGA Fabric Speed Grades

Gen4

x4 128-bit

350/400/450 ( Intel® Stratix® 10 DX)

350/400/450/500 (Intel Agilex® 7)

1

-1, -2 ( Intel® Stratix® 10 DX)

-1, -2, -3 (Intel Agilex® 7)

x8 512-bit

175/200/225 ( Intel® Stratix® 10 DX)

175/200/225/250 (Intel Agilex® 7)

1

-1, -2 ( Intel® Stratix® 10 DX)

-1, -2, -3 (Intel Agilex® 7)

x8 256-bit

175/200/225/350/400/ 450 ( Intel® Stratix® 10 DX)

175/200/225/250/350/ 400/450/500 (Intel Agilex® 7)

1

-1, -2 ( Intel® Stratix® 10 DX)

-1, -2, -3 (Intel Agilex® 7)

x16 512-bit

175/200/225/350/400 ( Intel® Stratix® 10 DX)

175/200/225/250/350/ 400/450/500 (Intel Agilex® 7)

1
-1, -2

( Intel® Stratix® 10 DX)

-1, -2, -3 (Intel Agilex® 7)

Gen3

x4 128-bit 250 -1, -2, -3

x8

256-bit 250 -1, -2, -3
x16 512-bit 250 -1, -2, -3
x16 256-bit 250 2 -1, -2, -3

The following table shows the typical resource utilization information for selected configurations.

The resource usage is based on the Avalon® -ST IP core top-level entity (intel_pcie_ptile_ast) that includes IP core soft logic implemented in the FPGA fabric.

Table 7.  Resource Utilization Information for the P-tile Avalon® Streaming Intel FPGA IP for PCI Express*
Link Configuration Device Family ALMs M20Ks Logic Registers
Gen4 x16, EP Intel® Stratix® 10 DX 3,191 0 10,255
Gen4 x16, EP Intel Agilex® 7 3,513 0 9,896

For details on the application clock frequencies that the IP core can support, refer to PHY Clock and Application Clock Frequencies.

1 Select the highest clock frequency to achieve maximum PCIe Gen4 bandwidth.
2 In this configuration, interface efficiency is traded off for lower interface width.