P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
Public
Document Table of Contents
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G.1. Margin Masks Overview

The official margin mask is provided in the following table for reference. These margin masks provide a risk assessment for the FPGA PCIe interfaces on Intel P-tile Avalon Streaming designs.

The validation data of the margin mask table is based on the Intel Whitley platform with an internal validation board (in PCIe slot B) that has a total insertion loss range of 21dB to 25dB (from lane0 to lane15). The margin mask provided is subject to change as your system design is not the same as the validation system.

Table 155.  Margin Mask Values for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express1 tick in horizontal (Timing) direction = 24mUI, 1 tick in vertical (Voltage) direction = 1mV
  Exp Num Part x Num Repetition Timing Margin Left (tick) Timing Margin Right (tick) Voltage Margin Up (tick) Voltage Margin Down (tick)
PCIe* 3.0 BER 1e-9

2x5

3x5

4x5

5x5

9.34

9.06

8.89

8.78

8.12

7.88

7.73

7.64

29.23

28.37

27.86

27.52

33.11

32.13

31.54

31.13

PCIe* 4.0 BER 1e-9

2x5

3x5

4x5

5x5

6.90

6.64

6.48

6.38

5.16

4.94

4.81

4.72

19.83

19.13

18.71

18.43

23.00

22.30

21.88

21.59

PCIe* 3.0 BER 1e-12

2x5

3x5

4x5

5x5

10.84

10.56

10.39

10.28

9.42

9.18

9.03

8.94

32.23

31.37

30.86

30.52

36.11

35.13

34.54

34.13

PCIe* 4.0 BER 1e-12

2x5

3x5

4x5

5x5

8.40

8.14

7.98

7.88

6.46

6.24

6.10

6.02

22.73

22.03

21.61

21.33

25.90

25.20

24.78

24.49