P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
Public
Document Table of Contents
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2.1.3.1. Independent PERST

The P-Tile Avalon Streaming Intel FPGA IP for PCIe allows further flexibility to handle an independent reset operation for each of the active PCIe cores for only Configuration Mode 1 (x8x8 EP and x8x8 TLP Bypass UP/UP).

When the Enable Independent Perst parameter is set in the IP Parameter Editor, the additional and new p<n>_cold_perst_n_i and p<n>_warm_perst_n_i interface signals become available.

Consider the following guidelines for handling independent reset operations:
  • p<n>_cold_perst_n_i input ports can trigger a cold reset per active core. This reset clears sticky bits and resets the port controller and PHY layer.
  • p<n>_warm_perst_n_i input ports can trigger a warm reset per active core. This reset does not clear the sticky bits but resets the port controller and PHY layer.
  • pin_perst_n has the highest priority for reset over the p<n>_cold_perst_n_i or p<n>_warm_perst_n_i ports.
  • When pin_perst_n is asserted (i.e., low), all active cores are in reset.
  • When pin_perst_n is deasserted (i.e., high), the p<n>_cold_perst_n_i input ports can be used to trigger a cold reset operation on each of the active cores independently.
  • When pin_perst_n is deasserted (i.e., high), the p<n>_warm_perst_n_i input ports can be used to trigger a warm reset operation on each of the active cores independently.
  • Usage of the p<n>_warm_perst_n_i to perform a warm reset to one of the active cores must happen only after the deassertion (i.e., high) of the corresponding p<n>_reset_status_n port. As an example, in the x8x8 configuration, in order to trigger an independent warm reset operation on p0_warm_perst_n_i, the p0_reset_status_n signal must be deasserted (i.e., high). A similar constraint applies to p<n>_cold_perst_n_i and p<n>_pld_clrphy_n_i.

For more details on the implementation of two independent PERST#, refer to Bifurcated Endpoint Support for Independent Warm Resets.