P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
Public
Document Table of Contents

A.2.2.4.4. Egress Control Vector (Offset 0x8)

Table 139.  Egress Control Vector
Bits Register Description Default Value Access
[31:0] Egress Control Vector 0x0 RO