P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
Public
Document Table of Contents
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4.12.2. Configuration Registers Access

The User Avalon® -MM interface provides access to the configuration registers and the IP core registers. This interface includes an 8-bit data bus and a 21-bit address bus (which contains the byte addresses).

There are two methods to access the configuration registers:
  • Using direct User Avalon® -MM interface (byte access)
  • Using the Debug (DBI) register access (dword access). This method is useful when you need to read/write the entire 32 bits at one time (Counter/ Lane Margining, etc.)