P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
Public
Document Table of Contents
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5.2. Core Parameters

Depending on which Hard IP Mode you choose in the Top-Level Settings tab, you will see different tabs for setting the core parameters.

Figure 52. Intel P-tile Avalon® -ST Top-Level IP Parameter Editor for a x16 Hard IP Mode If you choose a 1x16 or 1x8 mode (either Gen4 or Gen3), only the PCIe0 Settings tab will appear.
Note: You can enable the TLP Bypass mode in the Top-Level Settings tab of the IP Parameter Editor as shown in the figure below:
Figure 53. Enabling TLP Bypass Mode
Figure 54. Intel P-tile Avalon® -ST Top-Level IP Parameter Editor for a 2x8 Hard IP ModeIf you choose a 2x8 mode (either Gen4 or Gen3), the PCIe0 Settings and PCIe1 Settings tabs will appear.
Figure 55. Intel P-tile Avalon® -ST Top-Level IP Parameter Editor for a x4 Hard IP ModeIf you choose a x4 mode (either Gen4 or Gen3), the PCIe0 Settings, PCIe1 Settings, PCIe2 Settings and PCIe3 Settings tabs will appear.