P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/04/2023
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4.8. Hot Plug Interface (RP Only)

Hot Plug support means that the device can be added to or removed from a system during runtime. The Hot Plug Interface in the P-Tile IP for PCIe allows an Intel FPGA with this IP to safely provide this capability.

This section describes the signals reported by the on-board hot plug components in the Downstream Port. This interface is available only if the Slot Status Register of the PCI Express Capability Structure is enabled.

Refer to the Slot Status Register of the PCI Express Capability Structure for additional information.
Table 70.  Hot Plug Interface
Signal Name Direction Description Clock Domain EP/RP/BP
sys_atten_button_pressed_i I Attention Button Pressed. Indicates that the system attention button was pressed, and sets the Attention Button Pressed bit in the Slot Status Register. coreclkout_hip RP
sys_pwr_fault_det_i I Power Fault Detected. Indicates the power controller detected a power fault at this slot. coreclkout_hip RP
sys_mrl_sensor_chged_i I MRL Sensor Changed. Indicates that the state of the MRL sensor has changed. coreclkout_hip RP
sys_pre_det_chged_i I Presence Detect Changed. Indicates that the state of the card presence detector has changed. coreclkout_hip RP
sys_cmd_cpled_int_i I Command Completed Interrupt. Indicates that the Hot Plug controller completed a command. coreclkout_hip RP
sys_pre_det_state_i I

Indicates whether or not a card is present in the slot.

0 : slot is empty.

1 : card is present in the slot.

coreclkout_hip RP
sys_mrl_sensor_state_i I

MRL Sensor State. Indicates the state of the manually operated retention latch (MRL) sensor.

0 : MRL is closed.

1 : MRL is open.

coreclkout_hip RP
sys_eml_interlock_engaged_i I Indicates whether the system electromechanical interlock is engaged, and controls the state of the electromechanical interlock status bit in the Slot Status Register. coreclkout_hip RP