Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

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ID 683040
Date 6/14/2021
Public
Document Table of Contents

4.3.1. FPGA Factory Image Overview

The Intel® FPGA PAC N3000 has an on-board flash with two partitions (user and factory) for storing two FPGA image files known as user image and factory image. A new Intel® FPGA PAC N3000 is provided with the factory image in both factory and user partition of the flash.

After an OTSU, in 8x10G configuration, the Intel FPGA PAC N3000 is loaded with 8x10G image in both factory and user partition. While in 4x25G and 2x2x25G configurations, the Intel FPGA PAC N3000 is loaded with 2x2x25G in factory partition and 4x25G in user partition.

When the image in the user partition fails to load, the Intel® FPGA PAC N3000 reverts back and boots from factory partition. This factory image loaded into the user partition provides basic functionality to demonstrate all the interfaces including Ethernet and external memory interfaces.

The factory image includes the following Intellectual Property (IP) to support in the development of Accelerator Function (AF):
  • The PCIe IP core
  • The Core Cache Interface protocol (CCI-P) fabric
  • DDR4 memory interface controller IP
  • QDR4 memory interface controller IP
  • 10 or 25 GbE physical interface and MACs with pass-through connectivity between Intel® Ethernet Connection C827 Retimer and Intel® Ethernet Controller XL710-BM2
  • FPGA Management Engine (FME)
  • Nios® core to configure the Intel Ethernet Connection C827 Retimers
Figure 11. Example: Factory Image for 2x2x25G

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