Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

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ID 683040
Date 6/14/2021
Public
Document Table of Contents

1.1. Acronym List

Acronym Expansion Description
Intel® FPGA PAC Intel FPGA Programmable Acceleration Card Intel FPGA PAC N3000 is a full-duplex 100 Gbps in-system re-programmable acceleration card for multi-workload networking application acceleration.
AFU Accelerator Functional Unit Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.
AF Acceleration Function Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.
API Application Programming Interface A set of subroutine definitions, protocols, and tools for building software applications.
FIU FPGA Interface Unit FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe* and AFU-side interfaces such as CCI-P.
OPAE Open Programmable Acceleration Engine The OPAE is a set of drivers, utilities, and API's for managing and accessing AFs.
FME FPGA Management Engine The FME provides information about the FPGA platform including the OPAE version.
OTSU One-Time Secure Update Updates the Intel® MAX® 10 Board Management Controller (BMC) with new image files to enable the Root of Trust (RoT) features.
RSU Remote System Update

An RSU operation sends an instruction to the device to trigger a power cycle of the Intel FPGA PAC N3000 only. This will force reconfiguration from flash for either Intel® MAX® 10 BMC image (on devices that support it) or the FPGA image.

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