Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

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ID 683040
Date 6/14/2021
Public
Document Table of Contents

8.3. Ethernet Pause Flow Control

The Intel FPGA PAC N3000 supports pause frame operation for:
  • 25G as described in Flow Control section of 25G Ethernet Intel Arria 10 FPGA IP User Guide.
  • 10G as described in Flow Control section of Low Latency Ethernet 10G MAC Intel FPGA IP User Guide.
The pause frame generation and response to pause frame reception is disabled by default. You can read the current setting of pause frame generation using:
$ ethtool --show-pause npacf0g0l0
Pause parameters for npacf0g0l0:
Autonegotiate:	off
RX:		off
TX:		off
To turn on the pause frame generation:
  1. Set Pause Quanta: Configurable register used to set the desired delay time embedded in the pause frame packet requesting peer to stop transmitting for a period defined by the quanta. One quanta equals 512-bit times.
  2. Hold-off Quanta: Configurable register used to set the desired delay time between consecutive pause frames packets in quanta or 512-bit times.
  3. Pause Frame Enable: Allows you to enable or disable pause frame behavior using the ethtool.
In a multicard system, if you want to configure pause frame on only a single PCIe device, run the following command to find the device mapping for the specific FPGA PCIe:
ls -l /sys/class/fpga/intel-fpga-dev.*
Sample output:
/sys/class/fpga/intel-fpga-dev.0 -> ../../devices/pci0000:11/0000:11:00.0/0000:12:00.0/0000:13:09.0/0000:15:00.0/fpga/intel-fpga-dev.0
/sys/class/fpga/intel-fpga-dev.1 -> ../../devices/pci0000:ae/0000:ae:00.0/0000:af:00.0/0000:b0:09.0/0000:b2:00.0/fpga/intel-fpga-dev.1

To turn on the pause frame generation for only FPGA PCIe 15:00.0, replace the intel-fpga-dev.* with device instance id intel-fpga-dev.0 in below commands.

Example of setting pause frame generation:
# echo 200 > /sys/class/fpga/intel-fpga-dev.*/intel-fpga-fme.*/pac_n3000_net.*.auto/\
net/npacf0g0l0/tx_pause_frame_quanta
# cat /sys/class/fpga/intel-fpga-dev.*/intel-fpga-fme.*/pac_n3000_net.*.auto/\
net/npacf0g0l0/tx_pause_frame_quanta
0xc8
# echo 200 > /sys/class/fpga/intel-fpga-dev.*/intel-fpga-fme.*/pac_n3000_net.*.auto/\
net/npacf0g0l0/tx_pause_frame_holdoff
# cat /sys/class/fpga/intel-fpga-dev.*/intel-fpga-fme.*/pac_n3000_net.*.auto/\
net/npacf0g0l0/tx_pause_frame_holdoff
0xc8
# ethtool --pause npacf0g0l0 tx on
# ethtool --show-pause npacf0g0l0
Pause parameters for npacf0g0l0:
Autonegotiate:	off
RX:		off
TX:		on
Note: All Ethernet settings listed in this section are not persistent across power cycles or server reboots or rsu. After power cycle or server reboot or rsu, the Intel FPGA PAC N3000 returns to default settings. The rsu command causes change in the PCIe B:D.F value.

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