Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

ID 683040
Date 6/14/2021
Document Table of Contents

11. Single Event Upset (SEU)

The Intel Manufacturing Single Event Upset (SEU) testing of Intel® FPGA PAC N3000 provides the following results:
  • SEU events do not induce latch-up in Intel® FPGA PAC N3000.
  • No SEU errors have been observed in hard CRC circuits and I/O registers.
  • The cyclic redundancy check (CRC) circuit can detect all single-bit and multi-bit errors within the configuration memory.
SEU errors may occur in either of the two primary devices of the Intel® FPGA PAC N3000:
  • Intel® MAX® 10 SEU: An SEU event is detected by Error Detection CRC (EDCRC) circuitry in Intel® MAX® 10. The CRC function implemented in Intel® FPGA PAC N3000 enables CRC status to be reported to FPGA via a dedicated CRC_ERROR pin. The CRC error output is continually polled in an interval between 5.5 and 13.6 seconds.

    If a CRC error was detected, it is not permanently logged if subsequent polls do not detect an error.

    When FPGA detects a CRC_ERROR assertion, it is logged in the FPGA internal register RAS_CATFAT_ERR. The system register bits are not reliable after an SEU event, therefore a power cycle is required.

  • FPGA SEU: In FPGA device, the contents of the configuration RAM (CRAM) bits can be affected by soft SEU errors. The hardened on-chip EDCRC circuitry auto-detects CRC errors. Corrections of CRAM upsets are not supported. Therefore, if SEU errors are detected, FPGA reset is required.

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