Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Document Table of Contents

5.5. Parameterizing Native Fixed Point DSP IP

  1. In Intel® Quartus® Prime Pro Edition, create a new project that targets the Intel Agilex® 7 device.
  2. In IP Catalog, click Library > DSP > Primitive DSP > Native Fixed Point DSP Intel Agilex® FPGA IP.
    The Native Fixed Point DSP IP parameter editor opens.
  3. In the New IP Variation dialog box, enter an Entity Name and click OK.
  4. Under Parameters, select the operation mode, multiplier configuration, clear signal, port width, and internal coefficient configurations according to the variant of your IP core
  5. Click Generate HDL.
  6. Click Finish.