Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Document Table of Contents

2.2.5. Output Register Bank for Floating-point Arithmetic

The positive edge of the clock signal triggers the 48-bit (32 bits data and 16 bits exception flags) bypassable output register bank. This register is not reset after power up and may hold unwanted data. Use the CLR signal to reset the register before starting an operation.

Figure 14. Location of Output Register for FP32 Operation Modes
Figure 15. Location of Output Register for FP16 Operation Modes

The following variable precision DSP block signals control the output register per variable precision DSP block:

  • CLK
  • ENA[2..0]
  • CLR[1]